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Unlock next-gen hardware performance secrets for your HPC codes

  Wednesday 18 May 2016 at 9h00

  Conference       Cerfacs    

Register to : Nicolas.Monnier@cerfacs.fr

“Unlock next-gen hardware performance secrets for your HPC codes; enable SIMD AVX/AVX-512 vector parallelism with Intel code modernization tool »

Abstract:

Software must be optimized for SIMD vector parallelism to achieve scaled performance on modern hardware. The gap between unoptimized baseline and SIMD+thread parallel code performance is increasing every year. SIMD code modernization is not without cost, but new capabilities of OpenMP 4.x “explicit vectorization” and new Intel® “Vectorization Advisor” software tool make it possible to introduce efficient and portable SIMD parallelism without disrupting ongoing development. Even with perfect vectorization developers often have to additionally balance CPU/vectors/thread utilization vs. memory sub-system data bottlenecks. This problem is also addressed with new experimental Intel Advisor 2017 capabilities (like Automated Roofline).

Speaker Bio: 

Zakhar A. Matveev, PhD, is a Parallel Studio product architect in Intel SSG group. His current focus is SIMD vector parallelism and memory assistance tools. His professional interests are in the areas of high performance computing, parallel programming, computer graphics, code modernization, software design and usability.

CALENDAR

Friday

24

May

2024

🎓 PhD Defense: Théo DEFONTAINE

Friday 24 May 2024From 10h00 at 13h00

  Phd Thesis       JCA room, Cerfacs, Toulouse, France    

Monday

27

May

2024

🎓 PhD Defense: Thibault GIOUD

Monday 27 May 2024From 14h00 at 18h00

  Phd Thesis       Cerfacs, Toulouse, France    

Thursday

30

May

2024

Young PhD day (JDD2024@Cerfacs) – 30/05/2024

Thursday 30 May 2024From 9h00 at 17h00

  Journée des Doctorants       CERFACS     

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