Purpose of workshop
Take advantage of architectures with new programming paradigms
In recent years computation has been exposed to a widely growing heterogeneity of the types of used devices and their manufacturers. This trend is driven by the specialisation of devices to fit the needs of specific workloads, which in turn is the strategy to satisfy the ever-growing demand in compute power. Heterogeneity is present in both high-performance computing and consumer electronics. Today’s systems use a multitude of co-processors and accelerators, such as GPUs, TPUs, and FPGAs, in addition to the traditional CPU.
Getting the maximum achievable performance out of today's hardware is a fine balance between optimal use of underlying hardware features and using code that is portable, easily maintainable, and power-efficient. These factors don’t necessarily work in tandem. They require prioritizing based on user needs. It’s non-trivial for users to maintain separate code bases for different architectures. A standard, simplified programming model that can run seamlessly on scalar, vector, matrix, and spatial architectures will give developers greater productivity through increased code reuse and reduced training investment.
Researchers and engineers with HPC knowledge
28, 29, 30 March 2023
- 3 days with sessions training
- Program is available here
- Free but Mandatory, please send an email to email@example.com
The workshop takes place at CERFACS and course language is French and english.